This invention relates to electronic memory devices and more particularly to a sense amplifier for converting the output from a memory cell to a digital signal. The invention includes both a sense amplifier circuit and a method for sensing data from a memory cell and converting the data to a digital signal.
Random access memory devices comprise arrays of memory cells, each cell adapted to store one bit of data or information. A plurality of memory cells are connected together in a column by a complementary pair of conductors referred to as bit lines and the array of memory cells includes many such columns and associated bit line pairs. Each cell in a column is also connected to a conductor referred to as a word line by which the particular memory cell in the column may be selected for a read or write operation. The complementary pair of bit lines associated with each column of memory cells is connected to a write driver circuit used in writing or storing data to a selected memory cell in the column. Each complementary pair of bit lines is also connected to a column decoder circuit which enables one of the plurality of memory cell columns for a read operation. The output from the column decoder circuit comprises a single complementary pair of data lines.
The bit lines are used both to write data to a memory cell for storage in the cell and to read data previously stored in a cell. In a read operation, both bit lines are placed in an initial charge state. In this initial charge state both lines are typically charged to a supply voltage level. The memory cell selected in the read operation maintains the charge level on one bit line and corresponding data line from the column decoder, and allows the charge state on the complementary bit line and data line to decay. The full charge state on one bit line and corresponding data line and the lower charge state on the complementary bit line and data line represents binary data, either a "1" or a "0", which was previously stored in the selected memory cell. However, since the lower charge state develops gradually on the complementary bit line and data line, the signals present on the bit lines and data lines in a read operation are not true digital signals.
A sense amplifier is connected to the complementary pair of data lines for receiving the analog signal produced from a memory cell in a read operation. The sense amplifier amplifies and converts the analog signal on the data lines to a true digital signal. A differential sense amplifier produces a finite gain and develops the desired signal level relatively slowly. Since it develops the desired digital signal relatively slowly, a differential sense amplifier may recover from an error occurring on the bit line. In contrast, a dynamic sense amplifier produces an infinite gain and develops the desired digital signal level more quickly than a differential sense amplifier. Although operating faster, a dynamic sense amplifier cannot recover from an error occurring on the bit line. With either a differential sense amplifier or dynamic sense amplifier, the data or information represented by the desired digital signal must be stored to a latch circuit or other suitable arrangement to hold the data for a desired time. However, these external latch arrangements added complexity to the prior sense amplifier circuits.
U.S. Pat. No. 5,526,314 ("314 Patent") discloses a dual mode sense amplifier having an integral latch. The device disclosed in 314 Patent initially operated in a differential sense amplifier mode to sense the data present on the data lines and then switched to a dynamic sense amplifier mode. Although relatively faster than a differential sense amplifier, the dual mode sense amplifier disclosed in the 314 Patent still relied on the relatively slow differential sense amplifier operation for sensing the data on the data lines.